Ideal FET and Verilog-A

The hyperbolic tangent function is a beautiful S-shaped curve.  It smoothly transitions from -1 to +1.  By scaling, stretching, and shifting, it can serve a variety of modeling tasks, while having continuous derivatives, which is a most desirable feature in circuit simulators.  

Many years ago, my first use of tanh was to fit amplifier measured data for Output Power versus Input Power, and hence, the gain compression characteristic.  The curve-fitting result can be used in a spreadsheet representing the overall gain of a multi-stage amplifier.  Similarly, the DC current versus Input Power can be fit to a modified tanh function, and hence, be used as a systems model for the Power-Added-Efficiency of a power amplifier chain.

The hyperbolic tangent has long played a role in FET transistor models, from the  Curtice  to the Angelov models.

I have often wanted an ideal hypothetical FET model for investigating power amplifier simulations.  More recently, I have wanted such a model for oscillator simulations.  In both cases, desirable characteristics of the hypothetical device's bounded voltage and current behavior are:

While reading about world population growth, I stumbled into the Logistics Function.  See Wikipedia here .  It is a well known function among statistics folks, but I had not seen it before.  It is equivalent to a scaled version of the tanh function, but has a beautifully simple expression with 3 parameters, namely:

Playing with the function in a spreadsheet, it occurred to me that using two Logistics functions could represent a FET transconductance  versus gate voltage.   One function expresses going from zero to a nearly constant value, and a second, negated, function combined with the first returns the sum to zero.  Since the transconductance is the change in drain current over the change in gate voltage, integrating it results in an expression for the drain current as a function of gate voltage.

A third Logistics Function can be used to model drain current as a function of drain voltage, i.e., the Idss saturation curve.  Then, as in the traditional FET modeling approach, multiplying the gate voltage expression times the drain voltage expression gives an overall expression for the drain current as a function of both gate and drain voltages.

These slides illustrate the use of the Logistics Function in developing a drain current expression.  The ideal FET is initially developed using the Equation Component in QucsStudio.

Ideal_FET

The above Equation Component implementation is just fine in DC or linear AC (or S-parameter) simulations, and although it does work in the time domain (Transient) simulator, it is incredibly slow, to the point of being useless.  Happily, the answer is to code the model expressions in Verilog-A.  

Although Verilog appealed to me during my working life,  I never learned to use it, probably because it required a re-compile step for the simulator software that I couldn't do.  So, I put off giving it a try in QucsStudio, far too long.  It is amazingly straight forward to give it a try, starting with the template example file furnished in QucsStudio.  These slides show the built-in example file.

VerilogA_in_QucsStudio

The slides below show an implementation of the ideal FET in QucsStudio using Verilog-A.

Ideal_VerilogA_FET